| A11 | 1 • | 40 | A10 |
| A12 | 2 | 39 | A9 |
| A13 | 3 | 38 | A8 |
| A14 | 4 | 37 | A7 |
| A15 | 5 | 36 | A6 |
| CLK | 6 | 35 | A5 |
| D4 | 7 | 34 | A4 |
| D5 | 8 | 33 | A3 |
| D3 | 9 | 32 | A2 |
| D6 | 10 | 31 | A1 |
| Vcc | 11 | 30 | A0 |
| D2 | 12 | 29 | GND |
| D7 | 13 | 28 | RFSH |
| D0 | 14 | 27 | M1 |
| D1 | 15 | 26 | RESET |
| INT | 16 | 25 | BUSREQ |
| NMI | 17 | 24 | WAIT |
| HALT | 18 | 23 | BUSACK |
| MREQ | 19 | 22 | WR |
| IORQ | 20 | 21 | RD |
| Pin | Symbol | Description |
|---|---|---|
| 1 | A11 | Address Line 11 Output |
| 2 | A12 | Address Line 12 Output |
| 3 | A13 | Address Line 13 Output |
| 4 | A14 | Address Line 14 Output |
| 5 | A15 | Address Line 15 Output |
| 6 | CLK | Clock Input |
| 7 | D4 | Data Line 4 |
| 8 | D5 | Data Line 5 |
| 9 | D3 | Data Line 3 |
| 10 | D6 | Data Line 6 |
| 11 | Vcc | Power +5V |
| 12 | D2 | Data Line 2 |
| 13 | D7 | Data Line 7 |
| 14 | D0 | Data Line 0 |
| 15 | D1 | Data Line 1 |
| 16 | INT | Maskable Interrupt Input (Active Low) |
| 17 | NMI | Non-Maskable Interrupt Input (Active Low) |
| 18 | HALT | Halt State Output (Active Low) |
| 19 | MREQ | Memory Request Output (Active Low) |
| 20 | IORQ | Input/Output Request Output (Active Low) |
| 21 | RD | Read Request Output (Active Low) |
| 22 | WR | Write Request Output (Active Low) |
| 23 | BUSACK | Acknowledge Bus Request for DMA Output (Active Low) |
| 24 | WAIT | Wait Request Input (Active Low) |
| 25 | BUSREQ | Bus Request Input (Active Low) |
| 26 | RESET | Reset Input (Active Low) |
| 27 | M1 | Machine Cycle 1 Output (Active Low) |
| 28 | RFSH | Dynamic Memory Refresh Output (Active Low) |
| 29 | GND | Power Ground |
| 30 | A0 | Address Line 1 Output |
| 31 | A1 | Address Line 1 Output |
| 32 | A2 | Address Line 2 Output |
| 33 | A3 | Address Line 3 Output |
| 34 | A4 | Address Line 4 Output |
| 35 | A5 | Address Line 5 Output |
| 36 | A6 | Address Line 6 Output |
| 37 | A7 | Address Line 7 Output |
| 38 | A8 | Address Line 8 Output |
| 39 | A9 | Address Line 9 Output |
| 40 | A10 | Address Line 10 Output |
| Parameter | Value | Unit |
|---|---|---|
| Maximum Voltage (Vcc) | 6.0 | V |
| Clock Speed (Original Z-80) | 2 | MHz |
| A | Accumulator |
| F | Condition Flags |
| B & C | General Purpose 8-bit registers (may be used together as a 16-bit register) |
| D & E | General Purpose 8-bit registers (may be used together as a 16-bit register) |
| H & L | High & Low bytes of 16-bit Address Pointer Register |
| I | Interrupt Register - Holds upper 8 bits of memory address for vectored interrupt processing |
| R | Refresh Register - Automatically incremented for Dynamic Memory Refresh (read only) |
| IX & IY | 16-bit Index Registers |
| SP | 16-bit Stack Pointer Register |
| PC | A16-bit Program Counter Register |
| IFF | Interrupt Flip Flop Flag |
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.