TMS9918A - Video Display Processor (composite output)


RAS	1 •	40	XTAL2
CAS	2	39	XTAL1
AD7	3	38	CPUCLK
AD6	4	37	GROMCLK
AD5	5	36	COMVID
AD4	6	35	EXTVDP
AD3	7	34	RESET/SYNC
AD2	8	33	Vcc
AD1	9	32	RD0
AD0	10	31	RD1
R/W	11	30	RD2
GND	12	29	RD3
MODE	13	28	RD4
CSW	14	27	RD5
CSR	15	26	RD6
INT	16	25	RD7
CD7	17	24	CD0
CD6	18	23	CD1
CD5	19	22	CD2
CD4	20	21	CD3

Pin	Symbol	Description
1	RAS	VRAM row address strobe
2	CAS	VRAM column address strobe
3	AD7	VRAM address/data bus (least significant bit)
4	AD6	VRAM address/data bus
5	AD5	VRAM address/data bus
6	AD4	VRAM address/data bus
7	AD3	VRAM address/data bus
8	AD2	VRAM address/data bus
9	AD1	VRAM address/data bus
10	AD0	VRAM address/data bus (most significant bit)
11	R/W	VRAM write strobe
12	GND	ground
13	MODE	CPU interface mode select (usu. a CPU address line)
14	CSW	CPU-VDP write strobe
15	CSR	CPU-VDP read strobe
16	INT	CPU interrupt output
17	CD7	CPU data bus (least significant bit)
18	CD6	CPU data bus
19	CD5	CPU data bus
20	CD4	CPU data bus
21	CD3	CPU data bus
22	CD2	CPU data bus
23	CD1	CPU data bus
24	CD0	CPU data bus (most significant bit)
25	RD7	VRAM read data bus (least significant bit)
26	RD6	VRAM read data bus
27	RD5	VRAM read data bus
28	RD4	VRAM read data bus
29	RD3	VRAM read data bus
30	RD2	VRAM read data bus
31	RD1	VRAM read data bus
32	RD0	VRAM read data bus (most significant bit)
33	Vcc	supply voltage
34	RESET/SYNC	reset (active low; when above +9V, sync input for ext. video)
35	EXTVDP	external VDP input
36	COMVID	composite video output
37	GROMCLK	VDP output clock; XTAL/24
38	CPUCLK	VDP color burst frequency clock
39	XTAL1	crystal input
40	XTAL2	crystal input

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
XTAL frequency	10.738635 ± 0.05%	MHz
XTAL load capacitors	15 (min) 39 (max)	pF
VRAM size	4 or 16	KB
Number of colors	15 plus transparent
Number of sprites	32
Sprites per line	4

Notes

Bit order numbering is backwards. 0 is the MSB and 7 is the LSB.
Write to control register: set MODE high, write data byte, write destination register in the format 10000RRR.
Write to VRAM: set MODE high, write lower address bits, write upper address bits (with highest bits set to 01), set MODE low, write data bytes. Address autoincrements.
Read from status register: set MODE high, read byte.
Read from VRAM: write lower address bits, write upper address bits (with highest bits set to 00), set MODE low, read data bytes. Address autoincrements.
MODE determines the source or destination of a CPU read/write data transfer.

Control registers:

0	VDP option control bits (mode, external VDP enable)
1	VDP option control bits (4/16K RAM, BLANK, interrupt enable, mode, sprite size, magnification)
2	Name table base address (0-15)
3	Color table base address (0-255)
4	Pattern generator base address (0-7)
5	Sprite attribute table base address (0-127)
6	Sprite pattern generator base address (0-7)
7	Text color, backdrop color

Graphics modes:

Text mode	40x24 text positions, 6x8-pixel patterns, two colors, no sprites
Graphics I mode	32x24 tile positions, 8x8-pixel patterns, 256 possible patterns with 2 colors per pattern, sprites
Graphics II mode	32x24 tile positions, 8x8-pixel patterns, 768 possible patterns with 2 colors per row, sprites
Multicolor mode	64x48 solid 4x4-pixel blocks of any color, sprites

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.