6522


GND	1 •	40	CA1
PA0	2	39	CA2
PA1	3	38	RS0
PA2	4	37	RS1
PA3	5	36	RS2
PA4	6	35	RS3
PA5	7	34	RES
PA6	8	33	D0
PA7	9	32	D1
PB0	10	31	D2
PB1	11	30	D3
PB2	12	29	D4
PB3	13	28	D5
PB4	14	27	D6
PB5	15	26	D7
PB6	16	25	∅2
PB7	17	24	CS1
CB1	18	23	CS2
CB2	19	22	R/W
Vcc	20	21	IRQ

Pin	Symbol	Description
1	GND	ground
2	PA0	port A
3	PA1	port A
4	PA2	port A
5	PA3	port A
6	PA4	port A
7	PA5	port A
8	PA6	port A
9	PA7	port A
10	PB0	port B
11	PB1	port B
12	PB2	port B
13	PB3	port B
14	PB4	port B
15	PB5	port B
16	PB6	port B (pulse counting input for timer 2)
17	PB7	port B (controllable by timer 1)
18	CB1	port B control (shift register clock)
19	CB2	port B control (shift register data)
20	Vcc	supply voltage
21	IRQ	interrupt request output*
22	R/W	read/write select
23	CS2	chip select (active low)
24	CS1	chip select (active high)
25	∅2	phase-2 clock input
26	D7	data bus
27	D6	data bus
28	D5	data bus
29	D4	data bus
30	D3	data bus
31	D2	data bus
32	D1	data bus
33	D0	data bus
34	RES	reset (active low)
35	RS3	register select (address bus)
36	RS2	register select (address bus)
37	RS1	register select (address bus)
38	RS0	register select (address bus)
39	CA2	port A control
40	CA1	port A control

Parameter	Value	Unit
Maximum clock frequency	1 (NMOS) 14 (W65C22)	MHz

Notes

* In older chips, IRQ was an open drain output. In the W65C22S, it is fully driven.

Registers:

$00	Output register B (write), input register B (read)
$01	Output register A (write), input register A (read)
$02	Data direction register B
$03	Data direction register A
$04	Timer 1 latch LSB (write), timer 1 counter LSB (read)
$05	Timer 1 counter MSB
$06	Timer 1 latch LSB
$07	Timer 1 latch MSB
$08	Timer 2 latch LSB (write), timer 2 counter LSB (read)
$09	Timer 2 counter MSB
$0A	Shift register
$0B	Auxiliary control register
$0C	Peripheral control register
$0D	Interrupt flag register
$0E	Interrupt enable register
$0F	Same as register $01, but with no effect on handshake

Timer 1 can operate in one-shot mode or free-running mode (square wave).
Timer 2 can operate in one-shot mode or pulse-counting mode (counts negative pulses on PB6).
Counters for timers in one-shot or free-running mode decrement at the ∅2 clock rate.
The shift register is 8 bits wide, can shift in or out, and can generate its own clock or shift under the control of an external clock on CB1.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

Versatile Interface Adapter

Specifications

Notes